Synopsys Presentation: Achieve Higher Yield, Faster Ramp With Yield Explorer (Includes Lunch)

Monday, 3 Jun 2013 12pm - 1pm

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Achieve Higher Yield, Faster Ramp With Yield Explorer

Includes complimentary lunch provided by Synopsys

Presenter: John Kirkland, Yield Management CAE, Synopsys

Details: The growth in size, complexity and geometry irregularities of 28nm and below leading edge technology designs has led to continuously increasing yield loss driven by design and design-process systematic interactions. Learn how Yield Explorer accelerates yield ramp by bringing together design, fab, and test data to enable a fast and efficient methodology to quantify and calibrate the effect of hotspots and inline defect measurements on yield and scan diagnostics.

Presenter Biography: John Kirkland has a BS in Electrical Engineering from the University of Texas at Austin. He has 18 years of experience providing yield analysis solutions to customers through his work at KLA-Tencor, HPL, and Synopsys. His most recent work is in the area of fabless/foundry collaboration with volume diagnostics.

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